Layout and routing

Layout is where the schematic becomes a physical object, and where electronics starts to feel like craft. Two boards with identical schematics can behave completely differently: one works first time, the other resets randomly because a decoupling capacitor sits 20 mm from its chip. This lesson covers the PCB Editor from blank board to fully routed, with the reasons behind each decision.

Outline and setup

Start with the outline. In the PCB Editor, select the Edge.Cuts layer, then use Place > Rectangle (or the line tool) to draw a closed shape of 40 mm by 25 mm. The outline must be a closed loop with no gaps, or the fab cannot route it. Round the corners with a radius of about 2 mm: sharp corners crack and snag, and the router bit cannot cut an inside corner perfectly square anyway.

Before placing parts, open File > Board Setup. Under Design Rules > Constraints, set your fab's limits (more in lesson 5). Under Design Rules > Net Classes, create two classes:

Assign +5V and +3V3 to Power, and the router will then use the right width automatically.

Now bring in the parts with Tools > Update PCB from Schematic (key F8). All footprints drop in a pile, joined by thin lines called ratsnest lines that show which pads must be connected.

Placement comes first

Routing is mostly decided by placement. Spend more time here than on routing. Use this order:

1. Fixed things first. The USB-C connector goes on a short edge, centred or off-centre, with its opening past the board edge so a plug can reach it. The ESP32-C3-MINI-1 goes at the opposite end with its antenna overhanging the board edge or at least right at it. The module datasheet requires no copper, traces or components under or near the antenna area. Draw that region as a keep-out zone.
2. Power chain next. Put the LDO close to the USB connector, with its two 10 µF capacitors within about 3 mm.
3. Decoupling capacitors. Each 100 nF goes directly beside the pin it serves, with the shortest possible path: pin, capacitor, ground.
4. User parts. Button and LED near an edge you can reach. Pin headers along the long sides, at 2.54 mm pitch, so standard jumper wires fit.
5. Silkscreen later. Move text after routing.

Trace width from current

A trace is a resistor. Current through it heats the copper and drops some voltage, so thicker traces for more current. A widely used approximation is the IPC-2221 formula. For 1 oz (35 µm) copper on an outer layer, a trace about 0.3 mm wide carries about 1 A with a 10 °C temperature rise. This is an approximation: real results depend on board thickness, nearby copper, airflow and ambient temperature, so treat it as a minimum with margin.

This board draws well under 1 A, so thermal limits are no issue. We use 0.5 mm for power anyway because wider traces have lower resistance, are less likely to break under manufacturing tolerance, and are easier to route around vias. Signals carry a few milliamps and can be thin, but not thinner than 0.2 mm if you want a cheap, high-yield board.

Route with Route > Route Single Track (key X). Click on a pad, move, and click to place corners. Prefer 45 degree bends over 90 degrees: they are shorter, avoid sharp inside corners of copper that can etch unevenly, and leave more room for neighbouring traces.

Clearance, vias and layers

Clearance is the minimum air gap between copper of different nets. 0.2 mm is comfortable on a standard fab process, and it is larger for high voltages. Do not reduce it to the fab's absolute minimum unless you have to, because tight margins lower yield.

A via is a plated hole that connects copper between layers. Use it when a trace must cross another on the opposite layer, or to connect a ground pour on the top layer to the bottom. Each via costs a little inductance and uses space, so avoid vias in decoupling paths. Place them with Place > Via or press V while routing to switch layer and drop one.

Ground pour

A ground pour (or plane) is a large area of copper tied to ground. On a two-layer board, use the back layer almost entirely for ground and keep signals mostly on the front. A pour gives every part a short, low-resistance return path, shields signals from each other, and reduces the amount of copper etched away.

Use Place > Zone (or Add Filled Zone in some menus), click four corners around the board on B.Cu, and select net GND. Press B (Edit > Fill All Zones) to fill it. Add a few stitching vias around the edges and in open areas to connect the front-layer ground to the back. Never fill the zone under the module antenna; use the keep-out zone to prevent it.

Keeping noisy and sensitive apart

Switching regulators and fast edges create noise; analog inputs and radio parts are sensitive. Our LDO is not a switcher, so its noise is low, but the principle stays: separate things that make noise from things that listen. Keep the ESP32-C3 antenna region free, route GPIO wires away from it, and do not run a long digital signal parallel to another for many centimetres. Where two traces must cross, cross them on different layers at a right angle.

A note on USB differential pairs

USB data runs on two wires, D+ and D-, carried as a differential pair: the receiver looks at the difference between them, so noise that hits both equally cancels. USB 2.0 expects a 90 Ω differential impedance. The ESP32-C3 runs USB Full Speed (12 Mbit/s), which is forgiving on a short two-layer board. Keep both traces the same length (within about 1 mm), run them side by side with a constant gap, avoid vias in them, and keep them short (under about 30 mm). KiCad's Route > Differential Pair (key 6) routes both at once. Exact 90 Ω needs a specific trace width and gap that depends on your board stack; a fab's impedance calculator can give them if you need controlled impedance.